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首頁 > 產品服務 > Substrate系列 - 產品介紹
 
 
Substrate產品介紹
 
LLGA






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規格
Specification
1. 0.1~0.25mm 厚度銅合金
2. 表面處理:焊線或植金球面鍍鎳金,接腳面鍍鎳金或裸銅
3. 接腳間隔最少0.4mm
1. 0.1~0.25mm thickness Copper alloy
2. Surface finish: chip side Ni/Au plating for wire bonding or flip chip gold
2. bumping, lead side Ni/Au plating or bare copper.
3. Lead pitch 0.4mm MIN.
功能
Function
1. 導線架型的IC 載板
1. Lead frame base IC substrate
說明
Description
1. 不對稱的線路可以設計在導線架上,而且製作容易
2. 可以提升載板供應商良率
3. 可以提升封裝廠良率且降低成本
4. 有導線架產品的散熱性與導電性優勢
5. 通過第一級信賴度測試
1. Asymmetry pattern design is easier to archive in lead frame substrate .
2. Yield improvement for substrate supplier.
3. Yield improvement and cost effective for package house.
4. Keep advantage of heat and electrical transfer efficiency other than
4. laminate substrate.
5. Passed lever 1 reliability testing.
技術能力
Capability
1. 接腳間隔最少0.4mm
2. 晶片面線寬最少75um,線距最少100um
3. 兩面線路垂直距離最少150um
1. Lead pitch 0.4mm MIN.
2. Die side circuit: Line 75um MIN. Spacing 100um MIN.
3. Die side to lead side pattern spacing: 150um MIN.
 
 
ULGA





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規格
Specification
1. 載板厚度0.15mm~0.25mm
2. 表面處理:鎳鈀金、鎳金
1. Substrate thickness 0.15mm~0.25mm
2. Surface finish: Ni/Pd/Au; Ni/Au
功能
Function
1. 與LLGA相似的塑膠IC載板
1. Laminate base IC substrate similar to LLGA
說明
Description
1. 比LLGA 更有容易設計不對稱線路
2. 一般塑膠載板的封裝製程
3. 封裝高度可降至0.35mm
4. 晶片焊墊直接與下方PCB相連,因此保有良好的散熱性
1. Asymmetry pattern design and more flexible than LLGA.
2. Normal plastic substrate packaging process.
3. Package height can down to 0.35mm.
4. Within good heat transfer archived by chip directly adhered to copper pad
4. which connect to PCB.
技術能力
Capability
1. 在35um銅厚下,線寬最少50um;線距最少75um,精度 ±25um
2. 盲孔縱橫比1
3. 孔環最少50um
1. Line 50um MIN. Spacing 75um MIN. within copper thickness 35um,
1. tolerance ± 25um.
2. Blind via aspect ratio 1.
3. A/R 50um MIN.
 
 
TQFN





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規格
Specification
1. 載板厚度最少0.02mm
2. 載具厚度0.15mm或0.20mm
3. 表面處理:鎳金
1. Substrate thickness 0.02mm MIN.
2. Carrier thickness 0.15mm, 0.2mm.
3. Surface finish: Ni/Au
功能
Function
1. IC 載板
1. IC substrate
說明
Description
1. 有載具的IC載板
2. 微小超薄封裝
3. 封裝高度最少0.35mm
4. 提升載板供應商良率,既有的設備即可生產
5. 提升封裝廠良率,既有的設備即可生產
1. Substrate with metal carrier.
2. Tiny and ultra thin package.
3. Package height down to 0.35mm
4. Yield improvement and easier to manufacture for substrate supplier within
4. existence equipment.
5. Yield improvement and easier to handling for packaging house within
5. existence equipment.
技術能力
Capability
1. 線寬最少75um;線距最少75um,精度 ±15um
1. Line 75um MIN. Spacing 75um MIN. tolerance ± 15um.
 
 
Laminate substrate











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規格
Specification
1. 依客戶需求製作
1. As customer demand
功能
Function
1. 塑膠IC載板
1. Laminate IC substrate
說明
Description
1. 載板上設置壩體供CMOS感測晶片封裝 (PLCC)
2. 載板上設置凹槽供CMOS感測晶片封裝 (PLCC)
3. 載板上無設置壩體的CMOS感測晶片封裝 (CCM)
4. 記憶卡
5. 壩體上可設計有金線焊墊
6. 可設計半孔
7. 有蝕刻導電線製程
8. 孔上可設焊墊
1. Substrate with DAM for CMOS image sensor package (PLCC).
2. Substrate with cavity for CMOS image sensor package (PLCC).
3. Substrate without DAM for CMOS image sensor package (CCM).
4. Memory card
5. Finger on DAM
6. Half via process is available
7. Etching back process is available
8. Via in pad process is available
技術能力
Capability
1. 在35um銅厚下,線寬最少50um;線距最少75um,精度 ±25um
2. 盲孔縱橫比1
3. 最小鑽孔徑0.1mm,孔位精度 ±50um
4. 內層孔環最少100um;外層孔環最少50um
5. 防焊寬度最少125um
6. 防焊開口最少150um,誤差±50um,相對線路位置準度 ± 100um
7. 半孔徑最少0.35mm
8. 凹槽殘厚X ± 50um
1. Line 50um MIN. Spacing 75um MIN. within copper thickness 35um,
1. tolerance ± 25um.
2. Blind via aspect ratio 1.
3. Drill via size 0.1mm MIN. Positional accuracy ±50um
4. Inner A/R 100um MIN. Out-layer A/R 50um MIN.
5. Solder mask dam width 125um MIN.
6. Solder mask opening size 150um MIN. ± 50um, positional accuracy
6. ± 100um relative to copper pattern.
7. Half via size 0.35mm
8. Blind routing cavity with residual thickness X ± 50um